1. Field of the Invention
The present invention generally relates to an optical disk control chip with memory buses sharing apparatus, and more particularly to an optical disk control chip with SDRAM and flash memory buses sharing.
2. Description of the Related Art
As the requirement of consumer media electronic products increasing, in order to enhance the product competition, the concept of SoC (System On Chip, SoC) has become a trend. Due to the device integrated, the chip with SoC concept have less power consumption, greater heat dissipation, and better signal sending quality. Moreover, the concept of SoC is to put more and more devices into one single chip, so each device in this chip have to be integrated or reduced its size in order to meet the concept of SoC. With the integration of devices, the use of devices and substrates can be reduced. Due to the reduction of size of devices, the volume of chip is reduced, and also the package is reduced, so the cost of the chip designed with the concept of SoC can be reduced.
a well-known architecture of a multi-media player 100 as shown in FIG. 1, which comprises of a control unit 110, a MPEG (Moving Picture Experts Group) unit 120, an optical storage media 101, a video output interface 102, and an audio output interface 103. The control unit 110 further comprises a servo controller 112, and a microprocessor unit 114; the MPEG unit 120 further comprises a central processor unit (CPU) 121, a MPEG decoder 122, a video encoder 125, and a DA/AD converter (digital to analog/analog to digital converter, DAC/ADC) 126. The control unit 110 couples to a first synchronous dynamic random access memory (SDRAM) unit 116 and a first flash memory unit 118; the MPEG unit 120 couples to a second synchronous dynamic random access memory (SDRAM) unit 123 and a second flash memory unit 124.
A well-known multi-media player working flow chart is as the following: when optical storage media 101 is put into multi-media player 100, servo controller 112 drives the motor to readout disk data, these data are stored into the first SDRAM unit 116 then readout and decoded and stored back to the first SDRAM unit 116; these data are transmitted from the first SDRAM unit 116 to MPEG decoder 122, and then stored into the second SDRAM unit 123 then readout and decoded and stored back to the second SDRAM unit 123; finally, these data are streamed, the video data are transmitted to video encoder 125 and transfer to NTSC or PAL form and then displayed in video output interface 102, the audio data are transmitted to DAC/ADC 126 then output by audio output interface 103. During data decoding, microprocessor 114 and CPU 121 also access the first and second flash memory units 118 and 124.
In order to handle large data, servo controller 112, CPU 121, microprocessor 114 and MPEG decoder 122 of multi-media player 100 require much memory space respectively, as a result, synchronous dynamic random access memory unit 116 and 123 should contain numbers of synchronous dynamic random access memories (SDRAMs) for temporary storing a large data of programs and as a buffer in high speed for superior playing quality. These same working function pins of SDRAMs could share a same bus to reduce occupied space of pins. Otherwise, flash memory unit 118 and 124 of multi-media player 100 should contain numbers of flash memories for storing programs, user's defaults, and firmware. Similarly, these same working function pins of flash memories could share a same bus.
The respective relationship between processors and memories of multi-media player 100 is shown in FIG. 2. Microprocessor 114 and CPU 121 could directly command access requests to first and second flash memory unit 118 and 124 respectively. However, servo controller 112 and MPEG decoder 122, each one having many controllers or processors in it and lots of them could command access requests at the same time, as a result an arbiter (such as Arbiter 210, 220) is necessary, to arbitrate which one of these access requests has a priority and which one of these access requests is executed.
A well-known multi-media player with at least one SDRAM and at least one flash memory simultaneously could increase system performance. The advantage of flash memory is keeping data without refresh frequently, and the data, such as initial programs, firmware, and user's defaults, is not loss when system powers down; and taking the advantages of high speed access of SDRAMs, writing these data which is read from flash memory into SDRAMs when system powers on or before accessing the data in the flash memory, because data are executed in SDRAMs, the access speed and performance of system are both increased.
The flow chart is shown in FIG. 3:    310: reading data from flash memory;    320: writing data into SDRAMs; and    330: waiting for microprocessor to read and execute the data in SDRAM.
It is noticed that using large memories could store much more data but also occupy much more memory space.
It is also noticed that because of slow access speed of flash memories and fast access speed of SDRAM, programs or data stored in flash memory could cause lower system performance; thus, at most time, system accessing data or performing programs from SDRAM improves system performance. However, flash memories are accessed only when system powers on or when accessing user's defaults. When flash memories are not accessed, the idle buses of flash memories and un-used pins are also waste of systems. In a word, whether flash memories are accessed or not, system buses using efficiency is low.
As the descriptions above, the present invention provides an apparatus and a method for memory access of sharing buses. With this invention, controllers and processors of system could use the same SDRAM and flash memory units, so the numbers of memories and the memory space both are reduced. In addition, the SDRAMs and flash memories units could use the same memory buses, so the memory pin numbers are further reduced and the buses using efficiency increase.